Designing with AXI DMA, developing Linux kernel level drivers and user level applications for it, and transferring data over network

Educational package, containing example designs, hardware and software source code, videos and support.

AXI Multi-Channel DMA (with Scatter-Gather data transfer) and using it under Linux

Educational package, containing example designs, hardware and software source code, videos and support.

AXI stream and memory mapped interfaces, PS-PL data transfer, hardware-software data sharing and Linux kernel level driver development

Educational package with In-Person training for ZYNQ and ZYNQ Ultrascale+ devices, containing example designs, hardware and software source code, videos and also support.

AXI DRAM FIFO

An AXI stream FIFO which uses DRAM memory (MIG or PS side DRAM) as its memory instead of FPGA block memories, allowing to realize FIFOs with very large depth.

AXI DRAM to BRAM Bridge

Easy to use IP for transferring data between on FPGA block memories and any (PL side or PS side...) DRAM memory.

PCI Express connectivity

Easy to learn content allowing you to create your own FPGA design with a working PCI Express link to PC.

RGMII to AXI stream Bridge (providing low latency and low area usage) (with integrated MDIO configuration engine)

An easy-to-use RGMII to AXI stream bridge for any FPGA device that has a RGMII Gigabit Ethernet PHY connected to its programmable fabric.

FPGA Interfacing to AD1937, AD1938 and AD1939 Audio CODECs

Low-area footprint FPGA interface IP for Analog devices multi-channel audio CODECs with full control through integrated I2C interface

FPGA Interfacing to AD7616 ADC (in software mode)

Low-area footprint, FPGA IP for interfacing to AD7616 device with dual-spi connection in software mode with full control over all device configurations.

AXI multi-channel DMA-capable SPI controller

An AXI SPI controller which supports up to 16 SPI (each Master or Slave) channels concurrently. It contains a DMA engine for direct access to memory.

AXI multi-channel DMA-capable I2C controller

An AXI IIC controller which supports up to 16 IIC (each Master or Slave) channels concurrently. It contains a DMA engine for direct access to memory.